1. Field of the Invention
This invention relates to interposers, and, more particularly, to an interposer having conductive through holes and a method of manufacturing the interposer.
2. Description of Related Art
In a flip-chip packaging process, since the coefficients of thermal expansion (CTE) of a semiconductor chip and a package substrate differ from each other significantly, bumps around the semiconductor chip cannot be well bonded to corresponding contacts disposed on the package substrate, and the semiconductor chip is thus easily peeling from the package substrate. With the rapid increase of integrity of an integrated circuit, the stress generated by and the warpage occurred on the semiconductor chip and the package substrate are getting worse due to the CTE mismatch of the semiconductor chip and the package substrate. As a result, the reliability of the semiconductor chip and the package substrate becomes worse, and a reliability test often fails.
In order to solve the above problems, a process in which a semiconductor substrate acts as an interposer is brought to the market. In the process, a silicon interposer is disposed between a package substrate and a semiconductor chip. Since the silicon interposer and the semiconductor chip are made of similar materials, the problem occurred due to CTE mismatch is avoided.
FIGS. 1A to 1D are cross sectional views illustrating a method of manufacturing an interposer 1 according to the prior art.
As shown in FIG. 1A, an insulating layer 11 and a plurality of through-silicon vias (TSV) 14 are formed in a silicon substrate 10. As shown in FIG. 1A′, the through-silicon vias 14 are formed by forming through holes 100, forming the insulating layer 11 and a conductive layer 12 in the through holes 100 and on the silicon substrate 10, electroplating the conductive layer 12 with a copper layer 140, and removing the copper layer 140 on a surface of the silicon substrate 10, the conductive layer 12 and the insulating layer 11 after the through-silicon vias 14 are formed in the through holes 100.
As shown in FIG. 1B, a first redistribution layer (RDL) 13 is formed on an upper surface side 10a of the silicon substrate 10 and electrically connected to the through-silicon vias 14, for a semiconductor chip (not shown) or a package substrate (not shown) to be mounted thereon.
As shown in FIG. 1C, a lower surface side 10b of the silicon substrate 10 is thinned.
As shown in FIG. 1D, a second redistribution layer (RDL) 16 is formed on the lower surface side 10b of the silicon substrate 10 and electrically connected to the through-silicon vias 14, for a semiconductor chip (not shown) or a package substrate (not shown) to be mounted thereon.
In the method of manufacturing the interposer 1 according to the prior art, the silicon substrate 10 is very thick, and the through holes 100 thus have a great depth h, e.g., 100 to 500 um, and a radius of 100 to 200 um. Therefore, an electroplating process has to be performed in the through holes 100 for a long time, in order for the copper layer 140 to be formed on the hole walls and bottom portions of the through holes 100. Because the electroplating process is performed for a long time, the copper layer 140 formed on a surface of the silicon substrate 10 is very thick, and has a rough surface. As a result, an overburden 141 is likely formed around end surfaces of the through holes, as shown in FIG. 1A″.
According to the prior art, a chemical mechanical polishing (CMP) process is used to remove the copper layer 140 on the surface of the silicon substrate 10. However, it is unlikely to remove the copper layer 140 and the overburden 141 completely without the surface of the silicon substrate 10 penetrated, if the copper layer 140 is very thick. Hence, the prior art suffers from a long process time, a high cost of chemical fluid, and a complicated process.
However, how to solve the problems of the prior art is becoming an urgent issue in the art.